Non-volatile flash memory devices have been developed by the semiconductor integrated circuit industry for various applications such as computers and digital communications. A conventional non-simultaneous operation flash memory device typically includes a single fixed memory bank. A conventional simultaneous operation flash memory device typically comprises two fixed memory banks each comprising a fixed number of sectors of memory cells. Each sector of memory cells has a fixed amount of memory storage, for example, 0.5 megabytes (MB), and consists of a fixed number of pages of memory cells, for example, 16 pages of memory cells. A page is typically defined as one word of memory stored in the memory cells on a single word line.
In a conventional simultaneous operation flash memory device, for example, a conventional simultaneous operation NOR flash memory array, the NOR memory cells are divided into an upper memory bank and a lower memory bank each having a fixed size of memory storage. The upper and lower memory banks are typically used for different functions. For example, the upper memory bank may be used for code storage, whereas the lower memory bank may be used for data storage. Because the upper and lower bank memory partitions are fixed in conventional simultaneous operation flash memory devices, different simultaneous operation flash memory devices with different integrated circuit designs are required for different memory partitions. Therefore, in order to suit a variety of applications which may require different partitions of the upper and lower memory banks for code and data storage, new circuit designs would be required for different applications.
Because the size of memory storage in each of the upper and lower banks is not variable in a conventional simultaneous operation flash memory device, a single circuit design for a conventional simultaneous operation flash memory device may be suitable for only one of several different applications in which different partitions of the upper and lower memory banks are required. In order to produce simultaneous operation flash memory devices with different partitions of the upper and lower memory banks, a different circuit design and a full set of different masks are required for each of the devices. A disadvantage of having to design a different integrated circuit and a full set of different masks for each of the simultaneous operation flash memory devices with different upper and lower bank memory partitions is that the design, fabrication and testing processes can be very costly and time consuming. Therefore, there is a need for a simultaneous operation flash memory device with a flexible bank partition architecture. Furthermore, there is a need for a bank selector circuit for selecting the upper and lower memory banks in a simultaneous operation flash memory device with a flexible bank partition architecture in response to a memory address input.